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data sheet no.94710 page 1 of 33 01/31/05 ir3082pbf xphase tm amd opteron t m /athlon 6 4 tm control ic description the ir3082pbf control ic combined with an ir xphase tm phase ic provides a full featured and flexible way to implement a complete opteron or athlon64 pow er solution. the control ic provides overall system control and interfaces with any number of p hase ics which each drive and monitor a single phase of a multiphase converter. with simple 5 bit voltage programming and a few external components, the ir3082pbf is also well suited for general purpose multiphase applications. the xphase tm architecture results in a power supply that is smaller, less ex pensive, and easier to design while providing higher efficiency than conventional approaches. features ? 5 bit vid with 1% overall system set point accuracy ? programmable dynamic vid slew rate ? +/-300mv differential remote sense ? programmable 150khz to 1mhz oscillator ? programmable vid offset and load line output impedance ? programmable softstart ? programmable hiccup over-current protecti on with delay to prevent false triggering ? simplified power good output provides indicati on of proper operation and avoids false triggering ? operates from 12v input with 9.75v under-voltage lockout ? 7.0v/5ma bias regulator provides system reference voltage ? small thermally enhanced 20l mlpq package application circuit 5 wire analog bus (to phase ics) vss sense vcc sense power good 10 css/del 0.1uf rocset rosc rvfb 0.1uf rvdrp enable ir3082 pbf control ic vid0 1 vid1 2 vid2 3 vid3 4 vid4 5 pwrgd 19 vosns- 6 vdac 8 ss/del 18 rosc 7 enable 20 rmpout 17 lgnd 16 vcc 15 vbias 14 eaout 13 fb 12 vdrp 11 iin 10 ocset 9 cvdac vid3 vid4 vid0 vid2 vid1 12v rvdac downloaded from: http:///
ir3082p b f page 2 of 33 01/31/05 ordering inforamation device order quantity ir30 8 2 mtrpbf 3000 p er reel * IR3082MPBF 100 pi e c e str i ps * samples only absolute maximum ratings operating junction temperature..150 o c storage temperature range..-65 o c to 150 o c esd ratinghbm class 1b jedec standard pin # pin name v max v min i source i sink 1-5 vid0-4 20v -0.3v 1ma 1ma 6 vosns- 0.5v -0.5v 10ma 10ma 7 rosc 20v -0.5v 1ma 1ma 8 vdac 20v -0.3v 1ma 1ma 9 ocset 20v -0.3v 1ma 1ma 10 iin 20v -0.3v 1ma 1ma 11 vdrp 20v -0.3v 5ma 5ma 12 fb 20v -0.3v 1ma 1ma 13 eaout 10v -0.3v 20ma 20ma 14 vbias 20v -0.3v 50ma 10ma 15 vcc 20v -0.3v 1ma 50ma 16 lgnd n/a n/a 50ma 1ma 17 rmpout 20v -0.3v 1ma 1ma 18 ss/del 20v -0.3v 1ma 1ma 19 pwrgd 20v -0.3v 1ma 20ma 20 enable 20v -0.3v 1ma 1ma downloaded from: http:///
ir3082p b f page 3 of 33 01/31/05 electrical specifications unless otherwise specified, thes e specifications apply over: 9.6v v cc 16v, -0.3v vosns- 0.3v, 0 o c t j 100 o c, rosc = 24k ? , css/del = 0.1 f +/-10% parameter test condition min typ max unit vdac reference system set-point accuracy (deviation from table 1 per test circuit in figure 1 which emulates in-vr operation) 10k ? rosc 91k ? , rfb selected to provide 50mv vid offset -1 1 % source current includes ocset current 101 110 119 a sink current 92 100 108 a vidx input threshold 1.04 1.24 1.44 v vidx input bias current 0v vid0-4 vcc -5 0 5 a vidx 11111 blanking delay measure time till pwrgd drives low 0.5 0.7 1 s error amplifier input offset voltage measure v(fb) C v(vdac) with eaout tied to fb. applies to all vid codes. note 2. -5 1.5 6 mv fb bias current -53.5 -51 -48.5 a dc gain note 1 90 100 110 db gain bandwidth product note 1 6 10 mhz corner frequency 45 deg phase shift, note 1 400 hz slew rate note 1 1.4 3.2 5 v/ s source current 0.4 0.7 1 ma sink current 0.5 0.9 1.4 ma max voltage vbiasCveaout (refer enced to vbias) 250 375 525 mv min voltage normal operation or fault mode 30 125 200 mv vdrp buffer amplifier input offset voltage v(vdrp) C v(iin) -10 -1 6 mv source current 0.5v v(iin) 5v 1.2 3.0 5.0 ma sink current 0.5v v(iin) 5v 0.2 1.4 4.1 ma bandwidth note 1 1 6 mhz slew rate note 1 10 v/ s iin bias current -2 -0.3 0.4 a vbias regulator output voltage -5ma i(vbias) 0 6.6 7.0 7.4 v current limit -35 -20 -6 ma enable input threshold voltage enable rising 1.15 1.27 1.39 v threshold voltage enable falling 1.08 1.205 1.31 v threshold hysteresis 40 65 90 mv bias current 0v v(enable) vcc -5 0 5 a downloaded from: http:///
ir3082p b f page 4 of 33 01/31/05 note 1: guaranteed by design, but not tested in production note 2: vdac output is trimmed to compensate for error amp input offsets errors parameter test condition min typ max unit soft start and delay start delay (see fig 10) 1.2 1.9 2.6 ms soft start time (see fig 10) vid = 1. 3v (vid4-0 = 01010) 0.85 1.95 3.0 ms pwrgd delay (see fig 10) vid = 1.3v (vid4-0 = 01010) 1.0 2.0 3.0 ms oc delay time 150 250 350 us ss/del to fb input offset voltage with fb = 0v, adjust v(ss/del) until eaout drives high 0.95 1.3 1.6 v charge current 40 66 100 a discharge current 4 6 9 a charge/discharge current ratio 9.5 11 12.5 a/ a oc discharge current note 1 20 40 60 a charge voltage 3.65 3.9 4.15 v delay comparator threshold relative to charge voltage, ss/del rising 50 70 90 mv delay comparator threshold relative to charge voltage, ss/del falling 85 115 145 mv delay comparator hysteresis 15 35 50 mv discharge comparator threshold 175 225 275 mv over-current comparator input offset voltage -10 0 10 mv ocset bias current -54 -51.5 -49 a pwrgd output output voltage i(pwrgd) = 4ma 150 300 mv leakage current v(pwrgd) = 5.5v 0 10 a oscillator switching frequency 450 500 550 khz peak voltage (5v typical, measured as % of vbias) 70 71 74 % valley voltage (1v typical, measured as % of vbias) 10 13 15 % vcc under-voltage lockout start threshold 9.0 9.75 10.4 v stop threshold 8.4 9.0 9.6 v hysteresis start C stop 550 750 1150 mv general vcc supply current 8 10 12.5 ma vosns- current -0.3v vosns- 0.3v, all vid codes -4.5 -3.5 -2.5 ma downloaded from: http:///
ir3082p b f page 5 of 33 01/31/05 +- + "fast"vdac ioffset isink - isource error amp vdac buffer amp irosc irosc iocset current source generator rosc buffer amp + - 1.2v +- + - eaout vdac fb vosns- rosc ocset ir3082 rosc rvdac cvdac rfb system set point voltage figure 1 C system set point test circuit pin description pin# pin symbol pin description 1-5 vid4-0 inputs to vid d to a converter. 6 vosns- remote sense input. connect to ground at the load. 7 rosc connect a resistor to vosns- to program oscillator frequency and ocset, fb, and vdac bias currents. 8 vdac regulated voltage programmed by the vid inputs. connect an external rc network to vosns- to program dynamic vid slew rate and provide compensation for the internal buffer amplifier. 9 ocset programs the hiccup over-current thre shold through an external resistor tied to vdac and an internal current source. ov er-current protection can be disabled by connecting a resistor from this pin to vdac to program the threshold higher than the possible signal into the iin pin from t he phase ics but no greater than 5v (do not float this pin as improp er operation will occur). 10 iin current sense input from the phase ic(s ). if current feedback from the phase ics is not required for implementing droop or over -current protection connect to the lgnd pin. to ensure proper operat ion do not float this pin. 11 vdrp buffered iin signal. connect an external rc network to fb to program converter output impedance. 12 fb inverting input to the error amplifier. converter output voltage is offset from the vdac voltage through an external resistor connected to the converter output voltage at the load and an internal current source. 13 eaout output of the error amplifier. 14 vbias 6.8v/5ma regulated output used as a sys tem reference voltage for internal circuitry and the phase ics. 15 vcc power input for internal circuitry. 16 lgnd local ground for internal circuitry and ic substrate connection. 17 rmpout oscillator output voltage. used by phase ics to program phase delay 18 ss/del controls converter start-up and over-c urrent timing. connect an external capacitor to lgnd to program. 19 pwrgd open collector output that drives low during start-up and any external fault condition. connect external pull-up. 20 enable enable input. a logic low applied to this pin puts the ic into fault mode. do not float this pin as the logic state will be undefined. downloaded from: http:///
ir3082p b f page 6 of 33 01/31/05 system theory of operation xphase tm architecture the xphase tm architecture is designed for multiphase interleav ed buck converters which are used in applications requiring small size, design flexibility, low voltage, high current, and fast transient response. the architecture can be used in any multiphase converter ranging from 1 to 16 or more phases where flexibility facilitates the design trade-off of multiphase converters. the scalable architec ture can be applied to other applications which require high current or multiple output voltages. as shown in figure 2, the xphase tm architecture consists of a control ic and a scalable array of phase converters each using a single phase ic. the control ic communicates wi th the phase ics through a 5-wire analog bus, i.e. bias voltage, phase timing, average current, error amplifie r output, and vid voltage. the control ic incorporates all the system functions, i.e. vid, pwm ra mp oscillator, error amplifier, bias voltage, and fault protections etc. the phase ic implements the functions required by the converte r of each phase, i.e. the gat e drivers, pwm comparator and latch, over-voltage protection, and current sensing and sharing. there is no unused or redundant silicon with the xphase tm architecture compared to others such as a 4 phase controller that can be configured for 2, 3, or 4 phase operation. pcb layout is easier since the 5 wire bus eliminates the need for point-to-point wiring between the control ic and each phase. the critical gate drive and current sense connections are short and local to the phas e ics. this improves the pcb layout by lowering the parasitic inductance of the gate drive circuits and reducing the noise of the current sense signal. vr hot phase fault ccs cin rcs rcs ccs vdd_core 12v -sen gnd vid3 vid0 vid4 +sen vid2 pwrgd vid1 >> bias voltage >> vid voltage << current sense current share >> phase timing additional phases cout iru3082 control ic >> pwm control current share input/output iru3086a phase ic control bus iru3086a phase ic enable figure 2 C system block diagram downloaded from: http:///
ir3082p b f page 7 of 33 01/31/05 pwm control method the pwm block diagram of the xphase tm architecture is shown in figure 3. feed-forward voltage mode control with trailing edge modulation is used. a high-gain wide-bandwidth voltage type error amplifier in the control ic is used for the voltage control loop. an external rc circuit connected to the input voltage and ground is used to program the slope of the pwm ramp and to provide the feed-forward control at each phase. the pwm ramp slope will change with the input voltage and automatically compensate for changes in the input voltage. the input voltage can change due to variations in the silver box output voltage or due to drops in the pcb related to changes in load current. pwm comparator share adjust error amp rphs1 rvfb + - + - cscomp rphs2 + - + - rphs2 + - cpwmrmp x 0.9 + - cpwmrmp + - x 0.9 rphs1 + - + - + - rcs rpwmrmp + - ccs rcs + - ccs 10k +- rdrp +- cscomp + - vout gnd rpwmrmp vbias vdac biasin pwmrmp dacin vosns+ vosns- rampin+ rampin- ishare vosns- vdrp iin scomp gateh eain gatel csin+ csin- rmpout eaout fb vin biasin pwmrmp dacin rampin+ rampin- ishare scomp gateh eain gatel csin+ csin- 20mv irosc pwm comparator + + system reference voltage clock pulse generator enable ramp discharge clamp body braking comparator current sense amplifier pwm latch dominant reset s r x34 phase ic + - + + system reference voltage vbias regulator clock pulse generator enable ramp discharge clamp body braking comparator vdac vdrp amp ifb vpeak vvalley ramp generator 50% duty cycle current sense amplifier pwm latch dominant reset ramp slope adjust s r x34 error amp control ic cout share adjust error amp + - 10k 20mv + - phase ic ramp slope adjust figure 3 C ir3082pbf pwm block diagram frequency and phase timing control the oscillator is located in the control ic and its freq uency is programmable from 150 khz to 1mhz by an external resistor. the output of the oscillator is a 50% duty cycl e triangle waveform with peak and valley voltages of approximately 5v and 1v. this signal is used to program both the switch ing frequency and phase timing of the phase ics. the phase ic is programmed by resistor divider rramp1 and rramp2 connected between the vbias reference voltage and the phase ic lgnd pin. a comparator in the phase ics detects the crossing of the oscillator waveform with the voltage generated by the resistor divider and triggers a clock pulse that starts the pwm cycle. the peak and valley voltages track the vbias voltage reducing potential phase ic timing errors. figure 4 shows the phase timing for an 8 phase converter. note that both slopes of the triangle waveform can be used for synchronization by swapping the ramp+ and ramp- pins, as shown in figure 3. downloaded from: http:///
ir3082p b f page 8 of 33 01/31/05 ramp (fromcontrol ic) clk1 vvalley (1.00v) phase ic clock pulses vphase1&8 (1.5v) vphase3&6 (3.5v) vphase2&7 (2.5v) vphase4&5 (4.5v) vpeak (5.0v) clk2 50% ramp duty cycle clk3 clk4 clk5 clk6 clk7 clk8 slope = 80mv / % dc slope = 1.6mv / ns @ 200khz slope = 8.0mv / ns @ 1mhz figure 4 C 8 phase os cillator waveforms pwm operation the pwm comparator is located in the phase ic. upon re ceiving a clock pulse, the pwm latch is set, the pwmrmp voltage begins to increase, the low side driver is turned off, and the high side driver is then turned on. when the pwmrmp voltage exceeds the error amps output voltage the pwm latch is reset. this turns off the high side driver, turns on the low side driver, and activates the ramp discharge clamp. the clamp quickly discharges the pwmrmp capacitor to the vdac voltage of the control ic until the next clock pulse. the pwm latch is reset dominant allowing all phases to go to zero duty cycle within a few tens of nanoseconds in response to a load step decrease. phases can overlap and go to 100% duty cycle in response to a load step increase with turn-on gated by the clock pulses. an error amp output voltage greater than the common mode input range of the pwm comparator results in 100% duty cy cle regardless of the voltage of the pwm ramp. this arrangement guarantees the error amp is always in control and can demand 0 to 100% duty cycle as required. it also favors response to a load step decrease which is appropr iate given the low output to input voltage ratio of most systems. the inductor current will increase much more r apidly than decrease in response to load transients. this control method is designed to provide single cycle transient response where the inductor current changes in response to load transients within a single switching cycle maximizing the effectiveness of the power train and minimizing the output capacitor requirements. an additional advantage is that differences in ground or input voltage at the phases have no effect on operation sinc e the pwm ramps are referenced to vdac. downloaded from: http:///
ir3082p b f page 9 of 33 01/31/05 body braking tm in a conventional synchronous buck conver ter, the minimum time required to redu ce the current in the inductor in response to a load step decrease is; o min max slew v i i l t ) ( ? ? = the slew rate of the inductor current can be significant ly increased by turning off the synchronous rectifier in response to a load step decrease. the switch node voltage is then forced to decrease until conduction of the synchronous rectifiers body diode occurs. this increases t he voltage across the inductor from vout to vout + v body diode . the minimum time required to reduce the current in the inductor in respons e to a load transient decrease is now; bodydiode o min max slew v v i i l t + ? ? = ) ( since the voltage drop in the body diode is often higher than output voltage, the inductor current slew rate can be increased by 2x or more. this patent pending technique is referred to as body braking and is accomplished through the body braking comparator located in the phase ic. if the error amps output voltage drops below 91% of the vdac voltage this comparator turns off the low side gate driver. figure 5 depicts pwm operating waveforms under various conditions. phase ic clock pulse eain vdac pwmrmp gateh gatel steady-state operation duty cycle decrease due to vin increase (feed-forward) duty cycle increase due to load increase duty cycle decrease due to load decrease (body braking) or fault (vcc uv, ocp, vid=11111) steady-state operation 91% vdac figure 5 C pwm operating waveforms lossless average inductor current sensing inductor current can be sensed by connecting a series resist or and a capacitor network in parallel with the inductor and measuring the voltage across the capacitor. the equation of the sensing network is, cs cs l l cs cs l c c sr sl r si c sr s v s v + + = + = 1 )( 1 1 )( )( usually the resistor rcs and capacitor ccs are chosen so that the time constant of rcs and ccs equals the time constant of the inductor which is the inductance l over the inductor dcr (r l ). if the two time constants match, the voltage across ccs is proportional to the current through l, and the sense circuit can be treated as if only a sense resistor with the value of r l was used. the mismatch of the time constants does not affect the measurement of inductor dc current, but affects the ac component of the inductor current. downloaded from: http:///
ir3082p b f page 10 of 33 01/31/05 the advantage of sensing the inductor current versus high side or low side sensing is that actual output current being delivered to the load is obtained rather than peak or sampled information about the switch currents. the output voltage can be positioned to meet a load line based on real time information. except for a sense resistor in series with the inductor, this is the only sense method that can support a single cy cle transient response. other methods provide no information during eit her load increase (low side sensing) or load decrease (high side sensing). an additional problem associated with peak or valley current mode control for voltage positioning is that they suffer from peak-to-average errors. these errors will show in many ways but one example is the effect of frequency variation. if the frequency of a particular unit is 10% low, the peak to peak inductor current will be 10% larger and the output impedance of the converter will drop by about 10%. variations in inductance, current sense amplifier bandwidth, pwm prop delay, any added slope compensa tion, input voltage, and output voltage are all additional sources of peak-to-average errors. current sense amplifier a high speed differential current sense amplifier is located in the phase ic, as shown in figure 6. its gain decreases with increasing temperature and is nominally 34 at 25oc and 29 at 125oc (-1470 ppm/oc). this reduction of gain tends to compensate the 3850 ppm/oc increase in inductor dcr. since in most designs the phase ic junction is hotter than the inductor these two effects tend to cancel such that no additional temperature compensation of the load line is required. the current sense amplifier can accept positive differ ential input up to 100mv and negative up to -20mv before clipping. the output of the current sense amplifier is su mmed with the dac voltage and sent to the control ic and other phases through an on-chip 10k ? resistor connected to the ishare pi n. the ishare pins of all the phases are tied together and the voltage on the share bus represents t he total current through all the inductors and is used by the control ic for voltage positioning and current limit protection. l rl rcs ccs co + - cs am p csout figure 6 C inductor current sensing and current sense amplifier average current share loop current sharing between phases of the converter is achiev ed by the average current share loop in each phase ic. the output of the current sense amplifier is compared with the share bus less a 20mv offset. if current in a phase is smaller than the average current, the share adjust amplifier of the phase will activate a current source that reduces the slope of its pwm ramp thereby increasing its duty cy cle and output current. the crossover frequency of the current share loop can be programmed with a capacitor at the scomp pin so that the share loop does not interact with the output voltage loop. downloaded from: http:///
ir3082p b f page 11 of 33 01/31/05 ir3082p b f theory of operation block diagram the block diagram of the ir3082pbf is shown in figure 7 and discussed in the following sections. + - + disable eaout fb error amp ifb - isink isource vdac buffer amp + "fast" vdac + - +- 40ua dischg oc irosc irosc irosc +- vbias +- + - + - +- + - +- +- + - 1.270v + - + - 1.205v +- + - +- enable vosns- iin vid1 vcc ocset lgnd rosc vid2 vid0 vdac rmpout ss/del pwrgd vdrp vbias vid4 vid3 + - + - 6ua 50% duty cycle on 1.24v idischg 1.0v current source generator ramp generator 66ua on ss/del discharge oc comparator 7.0v vchg 3.9v softstart clamp 5.0v vbias regulator ichg vdrp amp rosc buffer amp 0.225v off 70mv current 700ns blanking digital to analog converter vcc uvlo comparator 9.75v enable comparator 9.0v iocset vid input comparators (1 of 5 shown) vid = off delay comparator discharge comparator over current +- fault latch r s set dominant ihiccup 1.3v 115mv figure 7 C ir3082pbf block diagram vid control a 5-bit vid voltage compatible with amds opteron/athlon64, as shown in table 1, is available at the vdac pin. the vid pins require an external bias voltage and should not be floated. the vid input comparators, with 1.2v reference, monitor the vid pins and control the 6 bit digi tal-to-analog converter (dac) whose output is sent to the vdac buffer amplifier. the output of the buffer amp is t he vdac pin. the vdac voltage is trimmed to compensate for the input offsets of the error amp to provide 1% system set-point accuracy and is pre-positioned 50mv higher than vout listed in table1 for load positioning. the actual vdac voltage does not determine the system accuracy and has a wider tolerance. the ir3082pbf can accept changes in the vid code while operating and vary the dac voltage accordingly. the sink/source capability of the vdac buffer amp is programmed by the same external resistor that sets the oscillator frequency. the slew rate of the voltage at the vdac pin can be adjusted by an external capacitor between vdac pin and the vosns- pin. a resistor connected in series wi th this capacitor is required to compensate the vdac buffer amplifier. digital vid transitions result in a smooth analog transition of the vdac voltage and converter output voltage minimizing inrush currents in the input and output capacitors and overshoot of the output voltage. downloaded from: http:///
ir3082p b f page 12 of 33 01/31/05 vid4 vid3 vid2 vid1 vid0 vout (v) 0 0 0 0 0 1.550 0 0 0 0 1 1.525 0 0 0 1 0 1.500 0 0 0 1 1 1.475 0 0 1 0 0 1.450 0 0 1 0 1 1.425 0 0 1 1 0 1.400 0 0 1 1 1 1.375 0 1 0 0 0 1.350 0 1 0 0 1 1.325 0 1 0 1 0 1.300 0 1 0 1 1 1.275 0 1 1 0 0 1.250 0 1 1 0 1 1.225 0 1 1 1 0 1.200 0 1 1 1 1 1.175 1 0 0 0 0 1.150 1 0 0 0 1 1.125 1 0 0 1 0 1.100 1 0 0 1 1 1.075 1 0 1 0 0 1.050 1 0 1 0 1 1.025 1 0 1 1 0 1.000 1 0 1 1 1 0.975 1 1 0 0 0 0.950 1 1 0 0 1 0.925 1 1 0 1 0 0.900 1 1 0 1 1 0.875 1 1 1 0 0 0.850 1 1 1 0 1 0.825 1 1 1 1 0 0.800 1 1 1 1 1 off 4 note: 4 output disabled (fault mode) table 1 C vid table adaptive voltage positioning adaptive voltage positioning is needed to reduce the output voltage deviations during load transients and the power dissipation of the load when it is drawing maximum current. the circuitry related to voltage positioning is shown in figure 8. resistor r fb is connected between the error amps invert ing input pin fb and the converters output voltage. an internal current source whose value is progra mmed by the same external resistor that programs the oscillator frequency pumps current into the fb pin. the error amp forces the conver ters output voltage lower to maintain a balance at its inputs. r fb is selected to program the desired amount of fixed offset voltage below the dac voltage. downloaded from: http:///
ir3082p b f page 13 of 33 01/31/05 the voltage at the vdrp pin is a buffered version of t he share bus and represents the sum of the dac voltage and the average inductor current of all the phases. the vdrp pin is connected to the fb pin through the resistor r vdrp . since the error amp will force the loop to maintain fb to be equal to the vdac reference voltage, current will flow into the fb pin equal to (vdrp-vdac) / r vdrp . when the load current increases, the adaptive positioning voltage increases accordingly. more current flows through the feedback resistor r fb , and makes the output voltage lower proportional to the load current. the positioning voltage can be programmed by the resistor r vdrp so that the droop impedance produces the desired converter output impedance. the offset and slope of the converter output impedance are referenced to and therefore independent of the vdac voltage. vdac rv drp rfb ishare vdac if b cs+ cs- ea vo vdrp iin phase ic vdac ishare cs+ phase ic cs- + - current sense amplifier 10k vdac ... ... fb error amplifier + - current sense amplifier + - + - control ic droop amplifier 10k figure 8 - adaptive voltage positioning inductor dcr temperature correction if the thermal compensation of the inductor dcr provided by the temperature dependent gain of the current sense amplifier is not adequate, a negative tem perature coefficient (ntc) thermistor c an be used for additional correction. the thermistor should be placed close to the inductor and connected in parallel with the feedback resistor as shown in figure 9. the resistor in series with the thermistor is used to reduce the nonlinearity of the thermistor. figure 9 - temperature com pensation of inductor dcr vdac rv drp rf b if b ea vdrp vo iin error amplifier + - + - control ic droop amplifier rf b rt fb downloaded from: http:///
ir3082p b f page 14 of 33 01/31/05 remote voltage sensing to compensate for impedance in the ground plane, the vosns- pin is used for remote sensing and connects directly to the load. the vdac voltage is referenced to vosn s- to avoid additional error terms or delay related to a separate differential amplifier. the capacitor connect ing the vdac and vosns- pins ensure that high speed transients are fed directly into the error amp without delay. soft start, over-current fault delay, and hiccup mode the ir3082pbf has a programmable soft-start function to limit the surge current during the converter start-up. a capacitor connected between the ss/del and lgnd pins controls soft start as well as over-current protection delay and hiccup mode timing. a charge current of 66ua and di scharge current of 6ua control the up slope and down slope of the voltage at the ss/del pin respectively . soft start-up waveforms are shown in figure 10. figure 11 depicts the various operating modes as controlle d by the ss/del function. if there is no fault, the ss/del pin will begin to be charged. the error amplifier output is clamped low until ss/del reaches 1.3v. the error amplifier will then regulate the converters output voltage to match the ss/del voltage less the 1.3v offset until it reaches the level determined by the vid inputs. the ss/del voltage continues to increase until it rises above 3.83v and allows the pwrgd signal to be asserted. ss/del finally se ttles at 3.9v, indicating the end of the soft start. under voltage lock out and vid=11111 faults as well as a low signal on the enable input immediately sets the fault latch causing ss/del to begin to discharge. the ss/del capacitor will continue to discharge down to 0.2v. if the fault has cleared the fault latch will be reset by the discharge comparator allowing a normal soft start to occur. a delay is included if an over-current condition occurs afte r a successful soft start sequence. this is required since over-current conditions can occur as part of normal operation due to load transients or vid transitions. if an over- current fault occurs during nor mal operation it will initiate the discharge of the capacitor at ss/del but will not set the fault latch immediately. if the ov er-current condition persists long enough for the ss/del capacitor to discharge below the 115mv offset of the delay comparator, the fault latch will be se t pulling the error amps output low inhibiting switching in the phase ic s and de-asserting the pwrgd signal. the delay can be reduced by adding a resistor in series with the delay capacitor. the delay comparators offset voltage is reduced by the drop in the resistor caused by the discharge curr ent. to prevent the charge current from creating an offset exceeding the ss/del to fb input offset voltage t he value of the resistor should be 10k ? or less to avoid interference with the soft start function. the ss/del capacitor will continue to di scharge until it reaches 0.2v and the fault latch is reset allowing a normal soft start to occur. if an ov er-current condition is again en countered during the soft star t cycle the fault latch will be set without any delay and hiccup mode will begin. during hicc up mode the 11 to 1 charge to discharge ratio results in a 9% hiccup mode duty cycle regardless of at what point the over-current condition occurs. if ss/del pin is pulled below 0.9v, the converter can be disabled. under voltage lockout (uvlo) the uvlo function monitors the ir3082pbfs vcc supp ly pin and ensures that ir3082pbf has a high enough voltage to power the internal circuit. the ir3082pbfs uvlo is set higher than the minimum operating voltage of compatible phase ics thus providing uvlo protection for them as well. during power-up the fault latch is reset when vcc exceeds 9.75v and there is no other fault. if the vcc voltage drops below 9.0v the fault latch will be set. for converters using a separate 5v supply for gate driver bias an external uvlo circuit can be added to prevent operation until adequate voltage is present. a diode connect ed between the 5v supply and the ss/del pin provides a simple 5v uvlo function. downloaded from: http:///
ir3082p b f page 15 of 33 01/31/05 over current protection (ocp) the current limit threshold is set by a resistor connec ted between the ocset and vdac pins. if the iin pin voltage, which is proportional to the average current plus da c voltage, exceeds the ocset voltage, the over-current protection is triggered. vid = 11111 fault vid code of 11111 will set the fault latch and disable the er ror amplifier. an 800ns delay is provided to prevent a fault condition from occurring during dynamic vid changes. power good output the pwrgd pin is an open-collector output and should be pull ed up to a voltage source through a resistor. during soft start, the pwrgd remains low until the output vo ltage is in regulation and ss/del is above 3.83v. the pwrgd pin becomes low if the fault latch is set. a high leve l at the pwrgd pin indicates that the converter is in operation and has no fault, but does not ensure the output voltage is within the specification. output voltage regulation within the design limits can logically be assur ed however, assuming no component failure in the system. load current indicator output the iin pin voltage represents the average current of the converter plus the da c voltage. the load current can be retrieved by subtracting the vdac voltage from the iin voltage. system reference voltage (vbias) the ir3082pbf supplies a 7.0v/5ma precision reference voltage from the vbi as pin. the oscillator ramp trip points are based on the vbias voltage so it should be used to program the phase ics phase delay to minimize phase errors. enable input pulling the enable pin below 1.27v sets the fault latch. downloaded from: http:///
ir3082p b f page 16 of 33 01/31/05 figure 10 C start-up waveforms figure 11 C operating waveforms vcc start-up normal operation hiccup over-currentprotection re-start after ocp clears power-down 9.0vuvlo (12v) enable ss/del 3.83v pwrgd vout iout (enable gates fault mode) (vcc gates fault mode) 1.3v (vout changes due to load and vid changes) o cp delay ocp threshold 3.785v vcc 9.0vuvlo 3.83v ss/del (12v) vout pwrgd enable (vtt) 1.3v start normal operation power-down soft start time 1.95ms (vcc uvl initiates fault mode) (enable ends fault mode) pwrgddelay 2.0ms start delay 1.9ms 1.27v downloaded from: http:///
ir3082p b f page 17 of 33 01/31/05 applications information dbst rosc cscomp l cin rphase11 cpwmrmp rcp cscomp ccs+ cin dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic 20k rbiasin rocset cvccl l l rpwmrmp dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic rfb1 cvcc dbst rphase53 rcs+ cvdac ccp rfb cbst dgate cscomp dbst 0.1uf cvcc l rcs+ ccs- cpwmrmp ccs+ rphase22 ccs+ rcs- ccs- rphase42 rpwmrmp rcs+ cin 10 ohm rvcc cbst rphase21 rcs- rpwmrmp cscomp rphase43 rphase13 qgate 0.1uf l rcs- ccs- dbst cbst rpwmrmp cpwmrmp cvccl cvcc rdrp ccs- ccs+ dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic rphase33 rpwmrmp 20k rbiasin rcs- 20k rbiasin dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic rphase23 rphase41 cin rcs+ rvdac rphase12 rphase52 rgate ccp1 dbst 20k rbiasin cscomp dacin 19 biasin 20 rmpin+ 1 rmpin- 2 gateh 14 vcch 15 csin- 17 phsflt 18 hotset 3 vrhot 4 scomp 6 eain 7 pgnd 13 gatel 12 lgnd 9 pwmrmp 8 ishare 5 vcc 10 vccl 11 csin+ 16 ir3086a phase ic rphase32 cvcc ccs+ cvccl rcs- cvccl rshare cbst rphase31 cbst cvcc cin rcs+ ccs- 20k rbiasin css/del cfb cvcc rphase51 cpwmrmp cpwmrmp cvccl phase fault vrhot powergood vout sense- vout sense+ vout+ enable vout- vid4 vid0 vid2 vid1 vid3 12v distribution impedance cout vid0 1 vid1 2 vid2 3 vid3 4 vid4 5 pwrgd 19 vosns- 6 vdac 8 ss/del 18 rosc 7 enable 20 rmpout 17 lgnd 16 vcc 15 vbias 14 eaout 13 fb 12 vdrp 11 iin 10 ocset 9 ir3082 control ic figure 12 C ir3082pbf/3086a 5 phase converter for opteron processor downloaded from: http:///
ir3082p b f page 18 of 33 01/31/05 performance characteristics figure 13 - oscillator frequency vs. rosc 150 250 350 450 550 650 750 850 950 1050 10 20 30 40 50 60 70 80 90 rosc (kohm) oscillator freq. (khz) figure 14 ifb, iocset vs. rosc 10 20 30 40 50 60 70 80 90 100 110 120 10 20 30 40 50 60 70 80 90 rosc (kohm) ua figure 15 - vdac source and sink currents vs. rosc 10 30 50 70 90 110 130 150 170 190 210 230 250 10 20 30 40 50 60 70 80 90 rosc (kohm) ua isource isink figure 16 - bias current accuracy vs. rosc 0 0.5 1 1.5 2 2.5 3 3.5 4 4.5 5 10 20 30 40 50 60 70 80 90 rosc (kohm) +/-3 sigma variation (%) fb , ocset b ias curr ent v da c sink curr ent vdac source current -50 0 50 100 150 200 gain phase figure 17 C error amplifier frequency response 10 100 1k 10k 100k 1m 10m 100m downloaded from: http:///
ir3082p b f page 19 of 33 01/31/05 design procedures C ir3082p b f and ir3086a chipset ir3082pbf external components oscillator resistor rosc the oscillator of ir3082pbf generates a triangle waveform to synchronize the phase ics, and the switching frequency of the each phase converter equals the oscillator frequency, which is set by the external resistor r osc according to the curve in figure 13. soft start capacitor c ss/del and resistor r ss/del because the capacitor c ss/del programs three different time parameters , i.e. soft start time, over current latch delay time, and the frequency of hiccup mode, they should be considered together while choosing c ss/del . the ss/del pin voltage controls the slew rate of the converter output voltage, as shown in figure 10. after the enable pin voltage rises above 1.23v, there is a soft-start delay time t ssdel , after which the error amplifier output is released to allow the soft start. the soft start time t ss represents the time during which the output voltage rises from zero to vo. t ss can be programmed by an external capacito r, which is determined by equation (1). o ss ss chg del ss v t t i c ? ? = ? = ? 6 o / 10 66 v (1) once c ss/del is chosen, the soft start delay time t ssdel , the over-current fault latch delay time t ocdel, and the delay time t vccpg from output voltage (vo) in regulation to power good are fixed and shown in equations (2), (3), (4) and (5) respectively. 6 / / 10 66 3.1 3.1 ? ? ? = ? = del ss chg del ss ssdel c i c t (2) 6 / / 10 6 09.0 09.0 ? ? ? = ? = del ss dischg del ss ocdel c i c t (3) 6 / / 10 66 )3.1 73.3( )3.1 73.3( ? ? ? ? ? = ? ? ? = o del ss chg o del ss vccpg v c i v c t (4) the hiccup mode duty cycle of over current protection is determined by the charge current i chg and discharge current i dischg of c ss/del and is fixed at 9%. however, the hiccup fr equency is determined by the load current and over-current set value. if faster over-current protection is required, a resistor in series with the soft start capacitor c ss/del can be used to reduce the over-current fault latch delay time t ocdel , and the resistor r ss/del is determined by equation (5). equation (1) for soft start capacitor c ss/del and equation (4) for power good delay time t vccpg are unchanged, while the equation for soft start delay time c ss/del (equation 2) is changed to equation (6). 6 / 6 / 10 6 10 6 09.0 09.0 ? ? ? ?? ? = ? ? = del ss ocdel dischg del ss dischg ocdel ssdel c t i c i t r (5) downloaded from: http:///
ir3082p b f page 20 of 33 01/31/05 6 6 / / / / 10 66 ) 10 66 3.1( ) 3.1( ? ? ? ? ? ? ? = ? ? ? = del ss del ss chg chg del ss del ss ssdel r c i i r c t (6) vdac slew rate programming capacitor c vdac and resistor r vdac the slew rate of vdac down-slope sr down can be programmed by t he external capacitor c vdac as defined in equation (7), where i sink is the sink current of vdac pin as shown in figure 15. the resistor r vdac is used to compensate vdac circuit and is determined by e quation (8). the slew rate of vdac up-slope sr up is proportional to that of vdac down-slope and is given by equation (9), where i source is the source current of vdac pin as shown in figure15. down sink vdac sr i c = (7) 2 15 10 2.3 5.0 vdac vdac c r ? ? + = (8) vdac source up c i sr = (9) over current setting resistor r ocset the inductor dc resistance is utilized to sense the inductor current. the copper wire of inductor has a constant temperature coefficient of 3850 ppm, and therefore the maximum inductor dcr can be calculated from equation (10), where r l_max and r l_room are the inductor dcr at maximum temperature t l_max and room temperature t_ room respectively. )] ( 10 3850 1[ _ 6 _ _ room max l room l max l t t r r ? ? ? + ? = ? (10) the current sense amplifier gain of ir3086a decrease s with temperature at the rate of 1470 ppm, which compensates part of the inductor dcr increase. the phase ic die temperature is only a couple of degrees celsius higher than the pcb temperature due to the low thermal impedance of mlpq package. the minimum current sense amplifier gain at the maximum phase ic temperature t ic_max is calculated from equation (11). )] ( 10 1470 1[ _ 6 _ _ room max ic room cs min cs t t g g ? ? ? ? ? = ? (11) the total input offset voltage (v cs_tofst ) of current sense amplifier in phase ics is the sum of input offset (v cs_ofst) of the amplifier itself and that cr eated by the amplifier input bias currents flowing through the current sense resistors r cs+ and r cs- . ? ? + + ? ? ? + = cs csin cs csin ofst cs tofst cs r i r i v v _ _ (12) the over current limit is set by the external resistor r ocset as defined in equation (13), where i limit is the required over current limit. i ocset, the bias current of ocset pin, changes with switching frequency setting resistor r osc and is determined by the curve in figure 14. k p is the ratio of inductor peak cu rrent over average current in each phase and is calculated from equation (14). ocset min cs tofst cs p max l limit ocset i g v k r n i r / ] ) 1( [ _ _ _ ? + + ? ? = (13) n i f vl v v v k o sw i o o i p / )2 /( ) ( ? ? ? ? ? = (14) downloaded from: http:///
ir3082p b f page 21 of 33 01/31/05 no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp a resistor between fb pin and the converter output is used to create output voltage offset v o_nlofst, which is the difference between v dac voltage and output voltage at no load condition. adaptive voltage positioning lowers the converter voltage by ro times io, where ro is the required output impedance of the converter. r fb is not only determined by i fb , the current flowing out of the fb pin as shown in figure 14, but also affected by the total input offset voltage of current sense amplifiers. r fb and r drp are determined by (15) and (16) respectively. max l fb o tofst cs nlofst o max l fb r i r n v v r r _ _ _ _ ? ?? ? ? = (15) o min cs max l fb drp r n g r r r ? ? ? = _ _ ( 16) ir3086a external components pwm ramp resistor r pwmrmp and capacitor c pwmrmp pwm ramp is generated by connecting the resistor r pwmrmp between a voltage source and pwmrmp pin as well as the capacitor c pwmrmp between pwmrmp and lgnd. choose the desired pwm ramp magnitude v ramp and the capacitor c pwmrmp in the range of 100pf and 470pf, and then calculate the resistor r pwmrmp from equation (17). to achieve feed-forward volt age mode control, the resistor r ramp should be connected to the input of the converter. )] ln( ) [ln( pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? ? ? ? = (17) inductor current sensing capacitor c cs+ and resistors r cs+ and r cs- the dc resistance of the inductor is utilized to se nse the inductor current. usually the resistor r cs+ and capacitor c cs+ in parallel with the inductor are chosen to match the time constant of the inductor , and therefore the voltage across the capacitor c cs+ represents the inductor current. if the tw o time constants are not the same, the ac component of the capacitor voltage is different from that of the real inductor current. the time constant mismatch does not affect the average current sharing among the multip le phases, but affect the cu rrent signal ishare as well as the output voltage during the load current transient if adaptive voltage positioning is adopted. measure the inductance l and the inductor dc resistance r l . pre-select the capacitor c cs+ and calculate r cs+ as follows. + + = cs l cs c rl r (18) the bias current flowing out of the non-inverting input of the current sense amplifier creates a voltage drop across r cs+, which is equivalent to an input offset voltage of the curr ent sense amplifier. the offs et affects the accuracy of converter current signal ishare as well as the accuracy of the converter output voltage if adaptive voltage positioning is adopted. to reduce the offset voltage, a resistor r cs- should be added between the amplifier inverting input and the converter output . the resistor r cs- is determined by the ratio of the bias current from the non-inverting input and the bias current from the inverting input. + ? + ? ? = cs csin csin cs r i i r (19) downloaded from: http:///
ir3082p b f page 22 of 33 01/31/05 if r cs- is not used, r cs+ should be chosen so that the offset voltage is small enough. usually r cs+ should be less than 2 k ? and therefore a larger c cs+ value is needed. over temperature setting resistors r hotset1 and r hotset2 the threshold voltage of vrhot comparator is proportional to the die temperature t j (oc) of phase ic. determine the relationship between the die temperature of phase ic and the temperature of the power converter according to the power loss, pcb layout and airflow etc, and then ca lculate hotset threshold voltage corresponding to the allowed maximum temperature from equation (20). 241 .1 10 73.4 3 + ? ? = ? j hotset t v (20) there are two ways to set the over temperature threshold, central setting and local setting. in the central setting, only one resistor divider is used, and the setting voltage is connected to hotset pins of all the phase ics. to reduce the influence of noise on the accuracy of over te mperature setting, a 0.1uf capacitor should be placed next to hotset pin of each phase ic. in the local setting, a resistor divider per phase is needed, and the setting voltage is connected to hotset pin of each phase. the 0.1uf decoupling capacitor is not necessary. use vbias as the reference voltage. if r hotset1 is pre-selected, r hotset2 can be calculated as follows. hotset bias hotset hotset hotset v v v r r ? ? = 1 2 (21) phase delay timing resistors r phase1 and r phase2 the phase delay of the interleaved multiphase converte r is programmed by the resistor divider connected at rmpin+ or rmpin- depending on which slope of the oscill ator ramp is used for the phase delay programming of phase ic, as shown in figure 3. if the upslope is used, rmpin+ pin of the phase ic should be connected to rmpout pin of the control ic and rmpin- pin should be connected to the resistor divi der. when rmpout voltage is above the trip voltage at rmpin- pin, the pwm latch is set. gatel becomes lo w, and gateh becomes high after the non-overlap time. if down slope is used, rmpin- pin of the phase ic should be connected to rmpout pin of the control ic and rmpin+ pin should be connected to the resistor divider. when rmpout voltage is below the trip voltage at rmpin- pin, the pwm latch is set. gatel becomes lo w, and gateh becomes high after the non-overlap time. use vbias voltage as the reference for t he resistor divider since the oscillator ramp magnitude from control ic tracks vbias voltage. try to avoid both edges of the oscilla tor ramp for better noise immunity. determine the ratio of the programming resistors, ra phasex , corresponding to the desired switching frequencies and phase numbers. if the resistor r phasex1 is pre-selected, the resistor r phasex2 is determined as: phasex phasex phasex phasex ra r ra r ? ? = 1 1 2 (22) combined over temperature and phase delay setting resistors r phase1 , r phase2 and r phase3 the over temperature setting re sistor divider can be combined with the phase delay resistor divider to save one resistor per phase. calculate the hotset threshold voltage v hotset corresponding to the allowed maximum temperature from equation (20). if the over temperature setting volt age is lower than the phase delay setting voltage, vbias*ra phasex , connect rmpin+ or rmpin- pin between r phasex1 and r phasex2 and connect hotset pin between r phasex2 and r phasex3 respectively. pre-select r phasex1, then calculate r phasex2 and r phasex3 , downloaded from: http:///
ir 30 8 2 pb f p age 23 of 33 01 / 31 / 0 5 ) 1( ) ( 1 2 p h a s ex b i as p h a s ex ho t s et b i as p h a s ex p h a s ex ra v r v v ra r - - = ( 23) ) 1( 1 3 p h a s ex b i as p h a s ex ho t s et p h a s ex ra v r v r - = ( 24) i f t he o v e r t e m pe r a t u r e s e t t i ng v o l t age i s h i ghe r t ha n t he pha s e de l a y s e tt i ng v o l t age , v b i as t i m e s ra p h as ex , c onne c t h o t s e t p i n be t w een r p h a se x 1 a nd r p h a s e x 2 and c o n ne c t r mp i n + o r r mp i n - be t w een r p h as e x 2 a nd r p h as e x 3 r e s pe c t i v el y . pr e - s e l e c t r p h ase x1 , ho t s et bias p h a s ex bias p h a s ex ho t s et p h a s ex v v r v ra v r - - = 1 2 ) ( ( 25) ho t s et bias p h a s ex bias p h a s ex p h a s ex v v r v ra r - = 1 3 ( 26) b oo t s t ra p ca p ac i t o r c b st depend i ng on t he du t y cy c l e and ga t e d r i v e c u rr en t o f t he pha s e i c , a 0 . 1u f t o 1u f c apa c i t o r i s needed f o r t he boo t s t r ap c i rc u i t . dec ou p l i n g ca p ac i t o rs f o r p h ase i c 0 . 1u f - 1u f de c oupl i ng c apa c i t o r s a r e r equ i r ed a t v c c and v ccl p i n s o f pha s e i c s . v o l t a g e l o o p c o m p e n s a tio n t he adap t i v e v o l t age po s i t i on i ng (a v p i s u s ua ll y u s ed i n t he c o m pu t e r appl i c a t i on s t o i m p r o v e t he t r a n s i en t r e s po n s e and r edu c e t he p o w e r l o ss a t he a v y l oad . l i k e c u rr en t m ode c on t r ol , t he adap t i v e v o l t age po s i t i on i n g l oop i n t r odu c e s e x t r a z e r o t o t he v o l t age l oop and s p li t s t h e doub l e po l e s o f t he po w e r s t age , wh i c h m a k e t he v o l t age l oop c o m pen s a t i on m u c h ea s i e r . re s i s t o r s r fb a n d r drp a r e c h o s en a cc o r d i ng t o e q u a t i on s ( 15 ) an d ( 16 ) , an d t he s e l e c t i on o f c o m pen s a t i on t y pe s depen d s on t he c apa c i t o r s u s ed . f o r t he appl i c a t i on s u s i ng e l e c t r o l y t i c , p o l y m e r o r a l -p o l y m e r c apa c i t o r s , t y pe i i c o m pen s a t i on s h o w n i n f i gu r e 18 ( a ) i s u s ua ll y enough . w hi l e f o r t he appl i c a t i on s w i t h on l y c e r a m i c c apa c i t o r s , t y pe i ii c o m pen s a t i on s h o w n i n f i gu r e 18 ( b ) i s p r e f e rr e d . ea o ut fbv d ac v o+ v d rp -+ e a o ut r fb r d rp r cp c cp c c p1 ea o ut fbv d ac v o+ v drp -+ ea o ut r f b1 c fb r fb rd rp r cp ccp c c p1 ( a ) t y p e i i c o m p e n s a t i on ( b ) t y p e i i i c o m p e n s a t i on f i gu r e 18 . v o l t age l oop c o m pen s a t i on ne t w o rk downloaded from: http:///
ir3082p b f page 24 of 33 01/31/05 type ii compensation determine the compensation at no load, the worst case condi tion. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, r cp and c cp can be determined by equations (27) and (28). o ce e c pwmrmp fb e e c cp v r c f v r c l f r ? ? ? ? + ? ? ? ? ? = 2 2 ) 2( 1 ) 2( (27) cp e e cp r c l c ? ? = 10 (28) where l e and r ce are the equivalent output inductance and esr of output capacitors respectively. c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. type iii compensation determine the compensation at no load, the worst case condi tion. choose the crossover frequency fc between 1/10 and 1/5 of the switching frequency per phase. assume the time constant of the resistor and capacitor across the output inductors matches that of the inductor, r cp and c cp can be determined by equations (29) and (30), where c e is equivalent output capacitance. o pwmrmp e e c cp v v c l f r ? ? ? ? = 2 ) 2( (29) cp e e cp r c l c ? ? = 10 (30) choose resistor r fb1 according to equation (31), and determine c fb from equations (32). fb fb r r 2 1 1 = to fb fb r r 3 2 1 = (31) 1 1 4 1 fb c fb r f c ? ? = (32) c cp1 is optional and may be needed in some applications to reduce the jitter caused by the high frequency noise. a ceramic capacitor between 10pf and 220pf is usually enough. current share loop compensation the crossover frequency of the current s hare loop should be at least one decade lower than that of the voltage loop in order to eliminate the interaction between the two loops. a capacitor from scomp to lgnd is usually enough for most of the applications. choose the cros sover frequency of current share loop (f ci ) based on the crossover frequency of voltage loop (f c ), and determine the c scomp , 6 _ 10 05.1 2 )] ( 2 1[ 65.0 ? ? ? ? ? ? ? ? + ? ? ? ?? ? = ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c (33) where fmi is the pwm gain in the current share loop, ) () ( dac i dac pwmrmp o pwmrmp sw pwmrmp pwmrmp scomp v v v v v v f c r c ? ? ? ? ? ? ? = (34) downloaded from: http:///
ir3082p b f page 25 of 33 01/31/05 design example D 5-phase opteron converter specifications input voltage: v i =12 v dac voltage: v dac =1.3 v no load output voltage offset: v o_nlofst =15mv maximum output current: i omax =100 adc output impedance: r o =0.75 m ? soft start time: t ss = 2 ms dynamic vid down-slope slew rate: sr down =2.5mv/us over temperature threshold: t pcb =115 oc power stage phase number: n=5 switching frequency: f sw =600 khz output inductors: l=220 nh, r l =0.42 m ? output capacitors: c=47uf, r c = 2m ? , number cn=32 ir3082pbf external components oscillator resistor rosc once the switching frequency is chosen, r osc can be determined from the curve in figure 13. for switching frequency of 600khz per phase, choose r osc =18.2k ? soft start capacitor c ss/del calculate the soft start capacitor from the required soft start time. uf v t i c o ss chg del ss 0988 .0 10 )15 50( 3.1 10 2 10 66 3 3 6 / = ? ? + ?? ? = ? = ? ? ? , choose uf c del ss 1.0 / = the soft start delay time is ms c i c t del ss dischg del ss ocdel 5.1 10 6 09.0 09.0 6 / / = ? ? = ? = ? ms i v c t chg o del ss vccpg 64.1 10 66 )3.1 335 .1 73.3( 10 1.0 )3.1 73.3( 6 6 / = ? ? ? ? ? = ? ? ? = ? ? vdac slew rate programming capacitor c vdac and resistor r vdac from figure 15, the sink current of vdac pin corresponding to 600khz (r osc =18.2k ? ) is 125ua. calculate the vdac down-slope slew-rate programming capacitor from the required down-slope slew rate. nf sr i c down sink vdac 50 10/ 10 5.2 10 125 6 3 6 = ? ? = = ? ? ? , choose c vdac =47nf calculate the programming resistor. ? = ? ? + = ? + = ? ? ? 2 ) 10 47( 10 2.3 5.0 10 2.3 5.0 29 15 2 15 vdac vdac c r downloaded from: http:///
ir3082p b f page 26 of 33 01/31/05 from figure 15, the source current of vdac pin is 170ua. the vdac up-slope slew rate is us mv c i sr vdac source up / 6.3 10 47 10 170 9 6 = ? ? = = ? ? over current setting resistor r ocset the room temperature is 25oc and the target pcb temperat ure is 100 oc. the phase ic die temperature is about 1 oc higher than that of phase ic, and the induct or temperature is close to pcb temperature. calculate inductor dc resistance at 100 oc, ? = ? ? ? +? ? = ? ? ? +? = ? ? ? m t t r r room max l room l max l 54.0 )]25 100 ( 10 3850 1[ 10 42.0 )] ( 10 3850 1[ 6 3 _ 6 _ _ the current sense amplifier gain is 34 at 25oc, and its gain at 101oc is calculated as, 2.30 )] 25 101 ( 10 1470 1[ 34 )] ( 10 1470 1[ 6 _ 6 _ _ = ? ? ? ? ? = ? ? ? ? ? = ? ? room max ic room cs min cs t t g g set the over current limit at 115a. from fi gure 14, the bias current of ocset pin (i ocset ) is 65ua with r osc =18.2k ? . the total current sense amplifier input offset vo ltage is 0.6mv, which includes the offset created by the current sense amplifier input resistor mismatch. calculate constant k p, the ratio of inductor peak current ov er average current in each phase, 147 .0 5/ 115 )2 10 600 12 10 220 /( 335 .1) 335 .1 12( / )2 /( ) ( 3 9 = ? ? ?? ? ? ? = ? ? ? ? ? = ? n i f vl v v v k limit sw i o o i p ocset min cs tofst cs p max l limit ocset i g v k r n r r / ] ) 1( [ _ _ _ ? + + ? ? = ? = ? ? ? + ? ? ? = ? ? ? k 9.6 ) 10 65 /(2.30 ) 10 6.0 147 .1 10 54.0 5 115 ( 6 3 3 no load output voltage setting resistor r fb and adaptive voltage positioning resistor r drp from figure 14, the bias current of fb pin is 65ua with r osc =18.2k ? . ? = ? ? ? ? ?? ? ? ? ? ? = ? ?? ? ? = ? ? ? ? ? ? 230 10 54.0 10 65 10 75.0 5 10 6.0 10 15 10 54.0 3 6 3 3 3 3 _ _ _ _ max l fb o tofst cs nlofst o max l fb r i r n v v r r select rfb = 232 ? . ? = ? ? ? ? ? = ? ? ? = ? ? k r n g r r r o min cs max l fb drp 01.1 10 75.05 2.30 10 54.0 232 3 3 _ _ downloaded from: http:///
ir3082p b f page 27 of 33 01/31/05 ir3086a external components pwm ramp resistor r ramp and capacitor c ramp set pwm ramp magnitude v pwmrmp =0.8v. choose 100pf for pwm ramp capacitor c pwmrmp , and calculate the resistor r pwmrmp , )] ln( ) [ln( pwmrmp dac in dac in pwmrmp sw in o pwmrmp v v v v v c f v v r ? ? ? ? ? ? ? = ? = ? ? ? ? ? ? ? ? ? = ? k 9.17 )]8.0 30.1 12 ln( )30.1 12 [ln( 10 100 10 600 12 30.1 12 3 , choose r pwmrmp =18.2k ? inductor current sensing capacitor c cs+ and resistors r cs+ and r cs- choose c cs+ =47nf and calculate r cs+, ? = ? ? ? = = ? ? ? + + k c rl r cs l cs 2.11 10 47 ) 10 42.0/( 10 220 9 3 9 choose ? = + k r cs 5.11 . the bias currents of csin+ and csin- are 0.25ua and 0.4ua respectively. calculate resistor r cs- , ? = ? ? = ? = + ? k r r cs cs 19.7 10 0.10 4.0 25.0 4.0 25.0 3 , choose r cs- =7.15k ? over temperature setting resistors r hotset1 and r hotset2 use central over temperature setting and set the temperat ure threshold at 115 oc, which corresponds the ic die temperature of 116 oc. calculate the hotset threshold voltage corresponding to the temperature thresholds. v t v j hotset 79.1 241 .1 116 10 73.4 241 .1 10 73.4 3 3 = + ? ? = + ? ? = ? ? , choose r hotset1 =20.0k ? , ? = ? ? ? = ? ? = k v v v r r hotset bias hotset hotset hotset 14.7 79.1 8.6 79.1 10 20 3 1 2 phase delay timing resistors r phase1 and r phase2 the phase delay resistor ratios for phases 1 to 5 at 600khz of switching fr equencies are raphase1=0.646, raphase2=0.400, raphase3=0.158, r aphase4=0.291 and raphase5=0.561 st arting from down-slope. pre- select rphase11=rphase21=rphase31= rphase41=rphase51= rphase61=20k ? , ? = ? ? ? = ? ? = k r ra ra r phase phase phase phase 5.36 10 20 646 .0 1 646 .0 1 3 11 1 1 12 r phase22 =13.3k ? , r phase32 =3.74k ? , r phase42 =8.2k ? , p phase52 =25.5k ? bootstrap capacitor c bst choose c bst =0.1uf decoupling capacitors for phase ic and power stage choose c vcc =0.1uf, c vccl =0.1uf downloaded from: http:///
ir3082p b f page 28 of 33 01/31/05 voltage loop compensation all ceramic output capacitors are used in the design, type iii compensation as shown in figure 18(b) is used here. choose the desired crossover frequen cy fc =80 khz and determine rcp and c cp : ? = ? ? ? ? ? ? ? ? ? = ? ? ? ? ? = ? ? k v v r c l f r o pwmrmp fb e e c cp 31.2 335 .1 8.0 230 )32 10 47()5/ 10 220 () 10 80 2( ) 2( 6 9 23 2 nf r c l c cp e e cp 2.35 10 31.2 )32 10 47()5/ 10 220 ( 10 10 3 6 9 = ? ? ? ? ? ? = ? ? = ? ? , choose c cp =33nf ? = ? = ? = 115 230 2 1 2 1 1 fb fb r r choose r fb1 =100 ? nf r f c fb c fb 54.8 100 10 80 4 1 4 1 3 1 = ? ? ? = ? ? = , choose c fb =10nf choose c cp1 =220pf to reduce high frequency noise. current share loop compensation the crossover frequency of the current share loop f ci should be at least one decade lower than that of the voltage loop f c . choose the crossover frequency of current share loop f ci =10khz , and calculate c scomp , 011 .0 )35.1 12()35.1 8.0 12( 8.0 10 600 10 100 10 2.18 ) () ( 3 12 3 = ? ? ? ? ? ? ? ? ? ? = ? ? ? ? ? ? ? = ? dac i dac pwmrmp i pwmrmp sw pwmrmp pwmrmp mi v v v v v v f c r f 6 _ 10 05.1 2 )] ( 2 1[ 65.0 ? ? ? ? ? ? ? ? + ? ? ? ?? ? = ci o mi o o e ci le room cs o i pwmrmp scomp f v f i v c f r g i v r c 6 3 4 4 6 3 3 3 10 05.1 10 10 2) 10 5.7 100 33.1( 011 .0] 100 ) 10 5.7 100 33.1( 10 1504 10 10 2 1[)5 10 42.0( 34 100 12 10 2.18 65.0 ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? + ? ? ? ? ? ? ? ? = ? ? ? ? nf 4.12 = choose c scomp =22nf downloaded from: http:///
ir3082p b f page 29 of 33 01/31/05 layout guidelines the following layout guidelines are recommended to reduce the parasitic inductance and resistance of the pcb layout, therefore minimizing the noise coupled to the ic. ? dedicate at least one middle layer for a ground plane lgnd. ? connect the ground tab under the control ic to lgnd plane through a via. ? place the following critical components on the same layer as control ic and position them as close as possible to the respective pins, r osc , r ocset , r vdac , c vdac , c vcc , c ss/del and r cc/del . avoid using any via for the connection. ? place the compensation components on the same layer as control ic and position them as close as possible to eaout, fb and vdrp pins. avoid using any via for the connection. ? use kelvin connections for the remote voltage sense si gnals, vosns+ and vosns-, and avoid crossing over the fast transition nodes, i.e. switching n odes, gate drive signals and bootstrap nodes. ? control bus signals, vdac, rmpout, iin, vbias, and especially eaout, should not cross over the fast transition nodes. downloaded from: http:///
ir3082p b f page 30 of 33 01/31/05 metal and solder resist ? the solder resist should be pulled away from the me tal lead lands by a minimum of 0.06mm. the solder resist mis-alignment is a maximum of 0.05mm and it is recommended that the lead lands are all non solder mask defined (nsmd). therefore pulli ng the s/r 0.06mm will alwa ys ensure nsmd pads. ? the minimum solder resist width is 0.13mm, theref ore it is recommended that the solder resist is completely removed from between the lead lands forming a single opening for each group of lead lands. ? at the inside corner of the solder resist where the lead land groups meet, it is recommended to provide a fillet so a solder resist width of 0.17mm remains. ? the land pad should be solder mask defined (smd), with a minimum overlap of the solder resist onto the copper of 0.06mm to accommodate solder resist mis-alignment. in 0.5mm pitch cases it is allowable to have the solder resist opening for the land pad to be smaller than the part pad. ? ensure that the solder resist in-between the lead lands and the pad land is 0.15mm due to the high aspect ratio of the solder resist strip separating the lead lands from the pad land. ? the single via in the land pad should be tented with solder resist 0.4mm diameter, or 0.1mm larger than the diameter of the via. downloaded from: http:///
ir3082p b f page 31 of 33 01/31/05 pcb metal and component placement ? lead land width should be equal to nominal part lead width. the minimum lead to lead spacing should be 0.2mm to minimize shorting. ? lead land length should be equal to maximum part lead length + 0.2 mm outboard extension + 0.05mm inboard extension. the outboard extension ensure s a large and inspectable toe fillet, and the inboard extension will accommodate any part misalignment and ensure a fillet. ? center pad land length and width should be equal to maximum part pad length and width. however, the minimum metal to metal spacing should be 0.17mm for 2 oz. copper ( 0.1mm for 1 oz. copper and 0.23mm for 3 oz. copper) ? a single 0.30mm diameter via shall be placed in t he center of the pad land and connected to ground to minimize the noise effect on the ic. downloaded from: http:///
ir3082p b f page 32 of 33 01/31/05 stencil design ? the stencil apertures for the lead lands should be approximately 80% of the area of the lead lands. reducing the amount of solder deposited will minimize the occurrence of lead shorts. since for 0.5mm pitch devices the leads are only 0.25mm wide, t he stencil apertures should not be made narrower; openings in stencils < 0.25mm wide are difficult to maintain repeatable solder release. ? the stencil lead land apertures should therefore be shortened in length by 80% and centered on the lead land. ? the land pad aperture should be striped with 0.25mm wide openings and spaces to deposit approximately 50% area of solder on the center pad. if too much solder is deposited on the center pad the part will float and the lead lands will be open. ? the maximum length and width of the land pad stencil aperture should be equal to the solder resist opening minus an annular 0.2mm pull back to decrease t he incidence of shorting the center land to the lead lands when the part is pushed into the solder paste. downloaded from: http:///
ir3082p b f page 33 of 33 01/31/05 package information 20l mlpq (5 x 5 mm body) C ja = 30 o c/w, jc = 3 o c/w data and specifications subject to change without notice. this product has been designed and qualified for the consumer market. qualification standards can be found on irs web site. ir world headquarters: 233 kansas st., el segundo, californi a 90245, usa te l: (310) 252-7105 tac fax: (310) 252-7903 visit us at www.irf.com for sales contact information . www.irf.com downloaded from: http:///

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